DocumentCode
2730779
Title
A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme
Author
Takai, Yoshiaki ; Fujita, Masayuki ; Nagata, Kazuyuki ; Isa, S. ; Nakazawa, Susumu ; Hirobe, A. ; Ohkubo, H. ; Sakao, M. ; Horiba, Shoichiro ; Fukase, T. ; Takaishi, Y. ; Matsuo, Michiaki ; Komuro, M. ; Uchida, Tomoyuki ; Sakoh, T. ; Saino, K. ; Uchiyama,
Author_Institution
NEC Corp., Kanagawa, Japan
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
418
Lastpage
419
Abstract
Describes a 1Gb double data rate (DDR) SDRAM which employs: 1) a clock generator that consists of a bidirectional delay (BDD), 2) a quadcoupled receiver (QCR), and 3) an inter-bank shared redundancy (ISR) scheme with a variable unit redundancy (VUR).
Keywords
DRAM chips; clocks; delays; redundancy; bi-directional delay; clock generator; double data rate SDRAM; inter-bank shared redundancy scheme; quadcoupled receiver; variable unit redundancy; Bidirectional control; Binary decision diagrams; Circuits; Clocks; Instruction sets; Logic; Microcomputers; National electric code; Propagation delay; SDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759333
Filename
759333
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