DocumentCode :
2730805
Title :
A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture
Author :
Kirihata, Toshiaki ; Mueller, G. ; Ji, Baojian ; Frankowsky, G. ; Ross, James ; Terletzki, H. ; Netis, D. ; Weinfurtner, O. ; Hanson, D. ; Daniel, Grivon ; Hsu, L. ; Storaska, D. ; Reith, A. ; Hug, Matthieu ; Guay, Kevin ; Selz, M. ; Poechmueller, P. ; Ho
fYear :
1999
fDate :
17-17 Feb. 1999
Firstpage :
422
Lastpage :
423
Abstract :
This 390mm/sup 2/ 16-bank 1Gb double-data-rate synchronous DRAM (DDR SDRAM) includes: (1) hybrid-bitline architecture; (2) hierarchical column-select operation; (3) hierarchical 8b prefetch; and (4) 1V swing single-ended read-write-drive (RWD) circuitry.
Keywords :
DRAM chips; MOS memory circuits; memory architecture; 1 Gbit; 1 V; 8 bit; DDR SDRAM; double-data-rate synchronous DRAM; hierarchical column-select operation; hierarchical prefetch; hybrid bitline architecture; single-ended read-write-drive circuitry; CMOS technology; Current measurement; DRAM chips; Packaging; Random access memory; SDRAM; Semiconductor device measurement; Solid state circuits; Very large scale integration; X-ray lithography;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
0-7803-5126-6
Type :
conf
DOI :
10.1109/ISSCC.1999.759336
Filename :
759336
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2730805
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