Title :
Partially-depleted SOI technology for digital logic
Author :
Shahidi, G.G. ; Ajmera, A. ; Assaderaghi, F. ; Bolam, R.J. ; Leobandung, E. ; Rausch, W. ; Sankus, D. ; Schepis, D. ; Wagner, L.F. ; Kun Wu ; Davari, B.
Author_Institution :
Microelectron. Div., IBM Corp., East Fishkill, NY, USA
Abstract :
This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remedies. A fully functional 32 bit microprocessor, operating at >500 MHz, demonstrates this SOI technology.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; integrated circuit design; integrated circuit technology; microprocessor chips; silicon-on-insulator; 0.25 micron; 32 bit; 500 MHz; PD SOI technology; Si; circuit design; device design; digital logic; microprocessor implementation; partially-depleted SOI technology; CMOS logic circuits; CMOS technology; Delay effects; Frequency; History; Microprocessors; Operating systems; Performance gain; Phase locked loops; Uncertainty;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759337
