DocumentCode
2730935
Title
A SOI specific PLL for 1 GHz microprocessors in 0.25 /spl mu/m 1.8 V CMOS
Author
Eckhardt, J.P. ; Muench, P.D.
Author_Institution
IBM Corp., Poughkeepsie, NY, USA
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
436
Lastpage
437
Abstract
A phase-locked loop (PLL) in silicon over insulator (SOI) for clock generation for CMOS processors can be used on all chips in a mainframe nest which constitute up to a 10-way computer. Test site measurements show a continuous range of operation between 65 MHz and 1.3 GHz with 12 ps steady-state jitter.
Keywords
CMOS digital integrated circuits; microprocessor chips; phase locked loops; silicon-on-insulator; timing circuits; timing jitter; 0.25 micron; 1 GHz; 1.8 V; 65 MHz to 1.3 GHz; CMOS processors; SOI specific PLL; Si; clock generation; mainframe nest; microprocessors; CMOS process; Clocks; Insulation; Jitter; Microprocessors; Phase locked loops; Semiconductor device measurement; Silicon on insulator technology; Steady-state; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759344
Filename
759344
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