Title :
Locally-clocked dynamic logic
Author :
Hoyer, Gregg ; Yee, Gin ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8×8 bit multiplier design that operates at 715 MHz in a 1.0 μm MOSIS process, which exceeds the highest multiplier frequency previously published
Keywords :
MOS logic circuits; clocks; integrated circuit design; logic CAD; logic gates; multiplying circuits; 1.0 micron; 715 MHz; 8 bit; MOSIS process; event-driven pipelines; localized clocking strategy; locally-clocked dynamic logic; multiplier design; robust dynamic gate design; throughput; CMOS technology; Circuits; Clocks; Delay effects; Frequency; Logic design; Logic devices; Pipelines; Space vector pulse width modulation; Throughput;
Conference_Titel :
Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-8914-5
DOI :
10.1109/MWSCAS.1998.759425
