Cu pillars on substrates — a low cost alternative for the next generation of Flip Chip packaging technology

As the stress coupling in organic Flip Chip packages become more critical due to the introduction of brittle materials and continued pitch shrink, various technologies are emerging to manage or reduce thermal mismatch stresses. In this regard pillar bumps on the die side have had a good start as they also address underfill flow at shrunk pitch as well as electromigration during operation. Pillar bumps on the substrate side is a worthy alternative as they can leverage the capabilities of the substrate industry. Pillar bump technologies such as Tessera´s μPILR^™ use a unique non -plating process to deposit bumps on substrates to create pillar bumps that are intrinsically co — planar, do not require solder on the bond pads and alter the crack initiation sites and propagation path favorably. These μPILR bumps are deposited on stock organic Flip Chip substrates using tools and processes commonly available to the PCB industry. Using build up panels with differing characteristics from three established suppliers of flip chip substrates, a 150 μm pitch version of μPILR technology has been developed at pilot plant level to a yield greater than 70 %. Units assembled with low — k die and substrates using several designs of μPILR interconnects and heat — spreaders have been tested for reliability (TC, EM) with encouraging results.