Title :
A VLSI switch architecture for broadband satellite networks
Author :
Wassal, A.G. ; Hasan, M.A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
In this paper, an ATM switch architecture is proposed for satellite on-board processing. The switch is based on a shared memory architecture for the switching fabric and a circular sorting queue for the buffer management unit. The design is constrained by both the network performance requirements and the limited payload of the satellite in terms of mass, area and power. A low-power ASIC implementation of the sorting queue that can support an aggregate traffic rate up to 21.2 Gbps is also presented
Keywords :
VLSI; application specific integrated circuits; asynchronous transfer mode; broadband networks; low-power electronics; satellite communication; shared memory systems; 21.2 Gbit/s; ATM switch; VLSI switch architecture; aggregate traffic rate; broadband satellite networks; buffer management unit; circular sorting queue; limited payload; low-power ASIC; network performance requirements; shared memory architecture; sorting queue; Aggregates; Application specific integrated circuits; Asynchronous transfer mode; Fabrics; Memory architecture; Payloads; Satellites; Sorting; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-8914-5
DOI :
10.1109/MWSCAS.1998.759431
