Fine pitch chip interconnection technology for 3D integration

3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption for next generation devices. For 3D chip integration, a robust micro-joining technology is required to stack Si chips, which usually offer high I/O pin counts to achieve better electrical performance. As for the 3D chip stacking methodology, chip-on-wafer bonding is expected to have higher yield than chip-on-chip or wafer-on-wafer bonding. In the case of chip-on-chip bonding, the large amount of bottom chip warpage induced by the printed circuit board during bonding causes a serious drop in the joining yield. Wafer-on-wafer bonding is limited by lower cumulative yield even though the throughput is very high. In this study, the chip-on-wafer bonding method is used for 3D chip stacking, and the 40um pitch interconnection technology is developed. Both fluxless thermo-compression and conventional flip chip bonding technique were adopted and evaluated for chip-on-wafer bonding. By optimizing the bonding conditions, the good bondability and electrical connections were achieved regardless of bonding technique.