Conductor technology for high density multilayer system

Author

Zorrilla, Marta L.

Author_Institution

BULL, Les Clayes Sous Bois, France

fYear

1988

fDate

13-15 Jun 1988

Firstpage

22

Lastpage

25

Abstract

Advanced high-speed, high-input/output-density integrated circuits (ICs) require model packaging techniques such as high-density multilayer polyimide-copper circuits on ceramic substrates populated with tape-automated-bonded IC chips. Thin-film techniques for pattern definition, polyimide deposition, and via etching are already well defined for multilayered modules. The compatibility of present thin-film techniques with conductor patterning methods is considered. Parametric test circuits with four metal layers have been fabricated and characterized. The minimal design rules were 25-μm lines on 50-μm pitch. The continuity of via chains of 20000 vias per chain was verified for 30-μm vias on 100-μm pitch

Keywords

hybrid integrated circuits; integrated circuit technology; metallisation; packaging; thin film circuits; 25 to 100 micron; conductor patterning; high density multilayer system; high-speed, high-input/output-density integrated circuits; metallisation; model packaging; thin-film techniques; via etching; Ceramics; Circuit testing; Conductors; High speed integrated circuits; Integrated circuit modeling; Integrated circuit packaging; Integrated circuit technology; Nonhomogeneous media; Substrates; Thin film circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Manufacturing Technology Symposium, 1988, Fourth IEEE/CHMT European International

Conference_Location

Neuilly sur Seine

Type

conf

DOI

10.1109/EEMTS.1988.75945

Filename

75945