Title :
A gain-compensated switched capacitor integrator
Author :
Fang, L. ; Chao, K.S.
Author_Institution :
Dept. of Electr. Eng., Texas Tech. Univ., Lubbock, TX, USA
Abstract :
A topology of switched capacitor integrator with gain compensation is proposed. It employs the same input as in the integrating phase during the calibration cycle to compensate for the integrating pole error due to the finite gain of the op-amp, and it eliminates the need of a “slow motion input” requirement. The proposed topology can be used, for example, in the switched capacitor implementation of sigma-delta modulators
Keywords :
calibration; integrating circuits; poles and zeros; switched capacitor networks; calibration cycle; finite gain; gain-compensated switched capacitor integrator; integrating pole error; sigma-delta modulators; slow motion input; Clocks; Delta modulation; Digital modulation; Feedback circuits; Material storage; Modulation coding; Phase modulation; Pulse modulation; Switched capacitor circuits; Switching circuits;
Conference_Titel :
Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-8914-5
DOI :
10.1109/MWSCAS.1998.759475
