Evaluating ASIC, DSP, and RISC architectures for embedded applications

Mathematical analysis and empirical evaluation of the solid state equation Power_CMOS=P=C·V² ·f·N·%N is presented in this paper which identifies a measurable metric for evaluating relative advantages of ASIC, DSP and RISC architectures for embedded applications. Relationships are examined which can help predict relative future architecture performance as new generations of CMOS solid state technology become available. In particular, performance/watt is shown to be an architecture-technology metric which can be used to: calibrate ASIC, DSP and RISC performance density potential relative to solid state technology generations; measure and evaluate architectural changes; and project an architecture performance density roadmap