Comparison of lidless & overmold flip chip package with 40nm ultra low-k Silicon Technology

Current portable electronic products are driving component packaging towards Flip Chip Packaging Technologies for integrating multiple electrical functionalities. The driver for flip chip continues to be performance and small form factor. This paper evaluates the lidless and molded flip chip packages with 40nm ultra low K (ULK) Silicon Technology. A comparative study on the two package types is carried out showing the effect of substrate core thickness and die thickness on the package coplanarity. Second level solder fatigue life between the two packages are also discussed. Finite Element Method (FEM) is done using various packaging design parameters and material properties for two packages types to study their effect on the key output parameters like stress in ULK Silicon, component and board level reliability.