DocumentCode
273240
Title
PICAP 3. A coarse-grained linear SIMD-array
Author
Danielsson, E. ; Lindskog, B. ; Segerström, Jan
Author_Institution
Linkoping Univ., Sweden
fYear
1988
fDate
11-15 Apr 1988
Firstpage
74
Lastpage
80
Abstract
Gives a brief description of the overall architecture of PICAP 3. The redesigned processor module has full floating-point arithmetic so that a 32 module machine will have a peak performance of 320 MFLOP. The authors show how the linear organization and the local address modification can be used efficiently for algorithms like FFT. Transposition, Matrix multiplication, Histogramming, Convolution and Binary image processing. PICAP 3 is orders of magnitudes faster than most commercially available systems
Keywords
parallel architectures; parallel machines; 320 MFLOPS; PICAP 3; SIMD-array; architecture; full floating-point arithmetic; linear organization; local address modification;
fLanguage
English
Publisher
iet
Conference_Titel
Design and Application of Parallel Digital Processors, 1988., International Specialist Seminar on the
Conference_Location
Lisbon
Print_ISBN
0-85296-366-1
Type
conf
Filename
10364
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