Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs

SRAM-based FPGAs are increasingly used in many applications. However, when used in critical embedded systems, their main drawback is the sensitivity of the configuration memory to external perturbations. Configuration errors can lead to erroneous results, but also to function modifications and SEFIs (Single Event Functional Interrupts). Consequences of configuration modifications must therefore be evaluated at design time to quantify the risk of critical application failures. In this paper, we briefly present a methodology developed and automated to answer this need. We also discuss on a set of design examples the influence of the design characteristics and of the FPGA architecture on the criticality of the configuration bits.