Self-Protecting Arrays for Open Drain Circuits

A new ESD protection strategy for NMOS arrays is described and experimentally evaluated. The problem of ESD protection of analog circuits has been addressed at the device/array level. Contrary to conventional rail-based or local clamp approaches this new concept provides for a self-protection capability into the array itself. The self-protecting capability of the NMOS array is achieved by embedding a local SCR region with reversible snapback capabilities and with a stronger dependence of the snapback voltage upon gate bias