High-speed pulse mode neural network with EE weights and on-chip learning (PMNN)

Summary form only given, as follows. An architecture and implementation of a pulse mode neural network with EE synapse weights, versatile interface capabilities, and on-chip learning are discussed. The interface has the ability to input data as 8-bit parallel bytes or as 64 parallel pulse streams. Output can be pulses (0-100 MHz) or 8-bit parallel data. The pulse mode neuron using nonvolatile electrically erasable programmable weights and a 100-MHz sigmoid voltage to frequency converter are also considered. Potential systems interfaces include a microprocessor peripheral interface. Various possible approaches and configurations for speech recognition and pattern recognition have been described