A 3.3 V high speed dual looped CMOS PLL with wide input locking range

Author

Sung, Hyuk-Jun ; Yoon, Kwang Sub ; Min, Hong Ki

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

fYear

1998

fDate

9-12 Aug 1998

Firstpage

476

Lastpage

479

Abstract

A 3.3 V PLL (Phase Locked Loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to frequency linearity of VCO (Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. PFD (Phase Frequency Detector) circuit preventing fluctuation of the charge pump circuit under the locked condition is presented. The simulation results of the PLL with a standard 0.6 μm CMOS technology illustrate a locking time of 3.5 μs±100 ps jitter and a power dissipation of 92 mW at 1 GHz operating frequency with 125 MHz of input frequency

Keywords

CMOS analogue integrated circuits; jitter; low-power electronics; phase detectors; phase locked loops; voltage-controlled oscillators; 0.6 micron; 3.3 V; 3.5 mus; 75.8 MHz to 1 GHz; 92 mW; PFD; VCO; charge pump circuit; dual looped CMOS PLL; input locking range; jitter; locking time; low power applications; operating frequency; phase frequency detector; power dissipation; voltage-to frequency linearity; CMOS technology; Charge pumps; Circuit simulation; Fluctuations; Jitter; Linearity; Low voltage; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-8914-5

Type

conf

DOI

10.1109/MWSCAS.1998.759534

Filename

759534