A 3.3 V high speed dual looped CMOS PLL with wide input locking range

A 3.3 V PLL (Phase Locked Loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to frequency linearity of VCO (Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. PFD (Phase Frequency Detector) circuit preventing fluctuation of the charge pump circuit under the locked condition is presented. The simulation results of the PLL with a standard 0.6 μm CMOS technology illustrate a locking time of 3.5 μs±100 ps jitter and a power dissipation of 92 mW at 1 GHz operating frequency with 125 MHz of input frequency