Title :
An approach to fast hierarchical fault simulation
Author :
Motohara, Akira ; Murakami, Motohide ; Urano, Miki ; Masuda, Yasuo ; Sugano, Masahide
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed.<>
Keywords :
circuit analysis computing; logic CAD; table lookup; behavioral description; fault insertion; hierarchical fault simulation; logic design environment; lookup tables; simulation-model generation; switch-level truth tables; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Delay; Semiconductor device modeling; Sequential circuits; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14845
