Identification of a Novel BTS and RVB Failure Mechanism in Copper/Ultra-Low k Integrations using a Stopless Trench Etch

We have discovered a novel failure mode in M2-M2 intralevel bias temperature stress (BTS) and ramp voltage breakdown (RVB) testing, in which the failure is mediated by shorting between the M2 and M1 metal layers. It has been observed in two copper/ultra-low k integration flows in the early stages of development. One integration used a chemical vapor deposition (CVD) carbon-doped oxide (CDO) while the other used a spin-on methylsilsequioxane (MSQ) dielectric; both integrations used stopless trench etch processes. In the CVD integration, the unexpected failure mode was caused by an interlevel dielectric thickness that was substantially thinner than expected. In the spin-on integration, it was caused by a trench etch and/or ash process that created deep microtrenches at the edges of 2 mum wide leads. This failure mode is possible whenever the two halves of the M2 comb structure overlay a single M1 feature