Noise analysis in hold phase for switched-capacitor circuits

Sample and hold (S/H) circuits play a key role in mixed-signal systems. Sample and hold noise is often the major bottleneck of S/H circuits used in high speed, high resolution applications. Invariably, designers consider only S/H noise contributed during the sampling phase of the switched-capacitor (SC) circuits. Continuous-time noise present during the hold phase is usually ignored. It is shown that continuous-time noise present during the holding phase is a significant contributor to the overall noise in high resolution and high speed circuits. Analytical formulations of the combined noise effects in popular switched-capacitor amplifiers are presented.