DocumentCode :
2733421
Title :
A vertical successive-approximation A/D converter architecture for high-speed applications
Author :
Hamdy, N. ; Soliman, H. ; Eid, A.
Author_Institution :
Coll. of Eng., AAST, Alexandria, Egypt
fYear :
1998
fDate :
9-12 Aug 1998
Firstpage :
542
Lastpage :
545
Abstract :
A non-iterative successive approximation quantization technique that provides high throughput rates at low decision cost/bit is described. The MSBs are obtained in a flash-like architecture operating according to a unidirectional successive approximation algorithm. The LSBs are then generated by recycling the built-in flash-type quantizer. Resolution is extendable at minimum speed loss through cascading similar stages operating with pipeline timing
Keywords :
analogue-digital conversion; approximation theory; timing; A/D converter architecture; flash-like architecture; flash-type quantizer; high throughput rates; high-speed applications; noniterative approximation quantization technique; pipeline timing; unidirectional successive approximation algorithm; vertical successive-approximation ADC; Approximation algorithms; Costs; Pipelines; Quantization; Recycling; Throughput; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-8914-5
Type :
conf
DOI :
10.1109/MWSCAS.1998.759550
Filename :
759550
Link To Document :
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