A Traffic Model for Concurrent Core Tasks in Networks-on-Chip

Network-on-Chip (NoC) is an emerging paradigm for design of VLSI/ULSI circuits. Communication bottleneck of traditional bus based systems has necessitated shift towards NoC framework. NoC consists of a communication layer of regularly placed routers connected to processing cores. NoC performance is determined by how it meets communication requirements of core applications and evaluated in terms of latency and throughput. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to multiple destinations. Need for such a traffic model arises as in a real-world scenario, an IP core is likely to execute multiple tasks concurrently, each task requiring communication with different destinations. The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistic demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core.