Title :
Winner-take-all circuit using CMOS technology
Author_Institution :
UNESP, Brazil
Abstract :
This paper presents an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 μA. The simulation also shows that the response time is 100 ns at a 0.2 pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD4007)
Keywords :
CMOS analogue integrated circuits; capacitance; circuit simulation; neural chips; unsupervised learning; CMOS technology; competitive learning; discrete CMOS transistor array; load capacitance; neural networks; response time; simulation results; winner-take-all circuit; CMOS technology; Capacitance; Circuit simulation; Computer networks; Delay; Neural networks; Speech; Testing; Unsupervised learning; Voltage;
Conference_Titel :
Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-8914-5
DOI :
10.1109/MWSCAS.1998.759556
