DocumentCode
2733536
Title
An evolvable artificial neural network platform for dynamic environments
Author
Merchant, Saumil G. ; Peterson, Gregory D.
Author_Institution
NSF Center for High-Performance Reconfigurable Comput., Florida Univ., Gainesville, FL
fYear
2008
fDate
10-13 Aug. 2008
Firstpage
77
Lastpage
80
Abstract
Dedicated hardware implementations of artificial neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, custom hardware implementations do not support intrinsic training of these networks on-chip. Training is typically done using software simulations and the obtained network is synthesized and targeted to hardware offline. The ANN FPGA design presented here facilitates dynamic network structure and parameter changes required for intrinsic training of artificial neural networks, without reliance on runtime FPGA reconfigurations. This is an important feature for an online trainable system as typical reconfiguration cycle times on the order of a few milliseconds pose to be a major performance bottleneck for iterative training algorithms. The designed platform implements block-based neural networks and can be evolved and adapted in-field.
Keywords
field programmable gate arrays; microprocessor chips; network-on-chip; neural nets; FPGA design; artificial neural network; dynamic environments; dynamic network structure; hardware implementations; iterative training algorithms; network on-chip; processors; software simulations; Application software; Artificial neural networks; Circuits; Computational modeling; Field programmable gate arrays; Network synthesis; Neural network hardware; Neural networks; Neurons; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location
Knoxville, TN
ISSN
1548-3746
Print_ISBN
978-1-4244-2166-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2008.4616740
Filename
4616740
Link To Document