Title :
Elimination of Single Event Latchup in 90nm SRAM Technologies
Author :
Puchner, H. ; Kapre, R. ; Sharifzadeh, S. ; Majjiga, J. ; Chao, R. ; Radaelli, D. ; Wong, S.
Author_Institution :
Technol. R&D, Cypress Semicond., San Jose, CA
Abstract :
We present a comprehensive review of design as well as process options to completely eliminate soft error induced single event latchup (SEL) in modern CMOS based SRAM technologies under datasheet operating conditions. The detailed mechanism of latchup under radiation environment is discussed and analyzed. EPI substrate starting material and the use of a triple well architecture are selected as process technology options to eliminate SEL. In addition to the process options we present a superior circuit option to quench out single event latchup. The options have been implemented on 90nm and validated on multiple experimental nuclear testing sites
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit testing; nanotechnology; radiation effects; 90 nm; CMOS based SRAM technologies; EPI substrate starting material; datasheet operating conditions; nuclear testing sites; radiation environment; soft error induced single event latchup elimination; Bipolar transistors; CMOS technology; Circuits; Current limiters; Neutrons; Power supplies; Random access memory; Substrates; Testing; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9498-4
Electronic_ISBN :
0-7803-9499-2
DOI :
10.1109/RELPHY.2006.251342
