DocumentCode :
2733634
Title :
MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip
Author :
Ebrahimi, Masoumeh ; Daneshtalab, Masoud ; Plosila, Juha ; Tenhunen, Hannu
Author_Institution :
Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
fYear :
2012
fDate :
5-8 Sept. 2012
Firstpage :
201
Lastpage :
207
Abstract :
While Networks-on-Chip have been increasing in popularity with industry and academia, it is threatened by the decreasing reliability of aggressively scaled transistors. This level of failure has architectural level ramifications, as it may cause an entire on-chip network to fail. Traditional fault-tolerant routing algorithms can overcome the faulty links or routers by rerouting packets around faulty regions. These approaches increase the packet latency and create congestion around the faulty region. In this paper, we present a novel fault-tolerant method that is able to route packets through shortest paths in the presence of faulty links, as long as a path exists. Although the same idea can be applied to a network with any number of virtual channels, we utilize two virtual channels to tolerate all one and two faulty links. Finally, the method is extended to support multiple faulty links by fully utilizing all allowable turns in the network.
Keywords :
fault tolerance; integrated circuit reliability; network routing; network-on-chip; MAFA; adaptive fault-tolerant routing algorithm; aggressively scaled transistor reliability; architectural level ramifications; faulty links; faulty regions; network-on-chip; packet latency; virtual channels; Artificial neural networks; Fault tolerance; Fault tolerant systems; Routing; System recovery; System-on-a-chip; fault-tolerant; minimal and adaptive routing algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location :
Izmir
Print_ISBN :
978-1-4673-2498-4
Type :
conf
DOI :
10.1109/DSD.2012.82
Filename :
6395726
Link To Document :
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