Sleep transistor sizing for multi-threshold-voltage network using Lagrange SOR iteration

The multi-threshold-voltage CMOS (MTCMOS) technique is very effective for reducing leakage power. Previously, sleep transistors were connected the virtual ground lines to reduce the power consumption, and a distributed sleep transistor network (DSTN) was proposed to reduce the instantaneous current. This paper presents a research on how to find the near optimal solution for the sleep transistor sizing problem in the DSTN structure. This paper adopts Lagrange successive over-relaxation (SOR) iterative method which is frequently used in the optimization field. The method makes sure the Lagrange multiplier satisfying the extreme conditions during the adjustment in each iteration, in order to find the near-optimum of the problem. Our experimental results are very exciting compared with the nonlinear programming.