High-sensitivity electromigration testing of lead-free WLCSP solder bumps

Miniaturization of consumer electronic devices is increasing demands to reduce the size of Power Management Integrated Circuit (PMIC) devices. In addition, the integration of additional functionality on a single chip is increasing the package´s I/O count. As a result, the packages for these devices are continuously reducing in size and lead pitch. The need to improve RON performance is pushing the capability limits of some of the current package solutions. The Wafer Level Chip Scale Package (WLCSP) is a viable option to meet these needs. This solution provides a small geometry, lightweight package with improved electrical and thermal performance compared to other available package technologies. However, as the WLCSP technology proliferates into new applications and markets, developers need to be continually aware of the limitations. For analog and power management devices, understanding the impact and limitations with the associated high current needs is imperative. Recent research is showing that as solder ball pitches and sizes decrease, the study of electromigration and solder joint reliability is crucial to ensuring the reliability of analog / PMIC devices in WLCSPs [1]. This paper summarizes recent work done to assess electromigration performance of lead-free WLCSP solder bumps.