The advanced pattern designs with electrical test methodologies on through silicon via for CMOS image sensor

The through silicon via (TSV) technology brings a key to 3D integration on wafer level packaging (WLP) by stacking chips to generate direct electrical interconnecting paths. Most of the related literatures employed the daisy chain test patterns to measure the electrical continuity and to evaluate the single via resistance. However, the single via resistance is actually the contact resistance between the two metal layers at the via bottom. In this paper, we developed new test patterns with suitable electrical measurement methodologies to evaluate several typical performance, including the contact resistance, on TSV with better accuracy.