DocumentCode :
2734093
Title :
An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology
Author :
Pranav, Pranav ; Giraud, Bastien ; Amara, Amara
Author_Institution :
Vellore Inst. of Technol. Univ. (VITU), Vellore
fYear :
2008
fDate :
10-13 Aug. 2008
Firstpage :
205
Lastpage :
208
Abstract :
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.
Keywords :
Monte Carlo methods; SRAM chips; ULSI; amplifiers; circuit reliability; low-power electronics; silicon-on-insulator; DG-SOI technology; Monte Carlo analysis; ULSI circuit; double-gate fully-depleted circuit; planar independent self-aligned gates; process variation insensitivity; reliability analysis; size 32 nm; ultra low voltage SRAM voltage sense amplifier; Circuits; Feedback; Low voltage; MOSFETs; Monte Carlo methods; Random access memory; Silicon on insulator technology; Threshold voltage; Ultra large scale integration; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
ISSN :
1548-3746
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2008.4616772
Filename :
4616772
Link To Document :
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