• DocumentCode
    2734151
  • Title

    An efficient architecture of RNS based Wallace Tree multiplier for DSP applications

  • Author

    Kundu, Partha Pratim ; Bandyopadhyay, Oishila ; Sinha, Amitabha

  • Author_Institution
    Sch. of Inf. Technol., West Bengal Univ. of Technol., Kolkata
  • fYear
    2008
  • fDate
    10-13 Aug. 2008
  • Firstpage
    221
  • Lastpage
    224
  • Abstract
    In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.
  • Keywords
    digital signal processing chips; multiplying circuits; RNS multiplier; Wallace tree multiplier; digital signal processing; optimal moduli set; residue number system; word length 32 bit; Adders; Arithmetic; Cities and towns; Complexity theory; Digital signal processing; Dynamic range; Electronic mail; Information technology; Performance analysis; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
  • Conference_Location
    Knoxville, TN
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-2166-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2008.4616776
  • Filename
    4616776
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2734151