A comparison of multiplierless multiple constant multiplication using common subexpression elimination method

The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we provide a comparison of hardware reductions achieved using the horizontal, vertical, oblique and combining horizontal and vertical CSEs in realizing constant multipliers. Our FPGA implementation results included in 52 MCM examples show that three different (horizontal, horizontal and vertical, and efficient horizontal and vertical) CSEs have a good area-time product performance, in the MCM matrix range of 800 and over.