Modeling, simulation and implementation of a passive mixer in 130nm CMOS technology and scaling issues for future technologies

In this paper, modeling, simulation, and implementation of double-balanced passive mixer are shown and examined. We analyze the performance of the mixer in terms of conversion gain (G_C), 1-dB compression point, and noise figure (NF). We will show the accuracy of our model and analyses when compared with simulation and measured results for a 130 nm technology based mixer design. We introduce a mixerpsilas figure-of-merit (FOM_MIXER) and briefly show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.