Image processing VLSI architecture based on data compression

To design low-power and high-speed image processors, the reduction of the number of interconnection units plays an important role. This paper presents a data-compression-based VLSI architecture that reduces the number of interconnection units between processing elements and memory modules without performance degradation. For example of a stereo matching VLSI, the number of interconnection units is reduced to 75%. The signal transition, which directly affects the dynamic power for data transfer, is also reduced to 50%.