Feasibility Study of a SiP for High Performance and Reliability Product Application

For specific applications, there can be significant performance advantages when using a SiP (system in package). With the proper silicon functional partitioning, well controlled interconnect medium, and well tuned interface design; the data bandwidth can be increased by both speed and width. The disadvantages of SiPs are increased risks in reliability, manufacturability, and difficulty with test access, repair, and rework. The subsystem within the package is a flipchip ASIC die, and four packaged memory components. This allows the memory to be tested at-speed and burned in prior to assembly in the SiP. The feasibility study resulted in a combination of physical design tradeoffs, and reliability assessment of a test vehicle. The substrates were evaluated for routability, signal and power integrity. A custom electrical interface was specified for the chips to maximize bandwidth of the system. Package coplanarity, thermal mechanical integrity, and long term reliability were also examined. Preliminary results were presented