A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems

Author

Weerasekera, Roshan ; Liu, Jian ; Zheng, Li-Rong ; Tenhunen, Hannu

Author_Institution

Lab. of Electron. & Comput. Syst., KTH Microelectron. & Inf. Technol., Kista

fYear

2005

fDate

27-29 June 2005

Firstpage

1

Lastpage

4

Abstract

Recent results showed that when the minimum feature size used in semiconductor device fabrication moves to sub nanometre scale, several physical and economic limits jeopardize the device behaviour, binary logic, and the lithography techniques currently used. To surpass this "brick-wall" and continue the Moore\´s law forever, novel nano-electronic devices are becoming more popular and promising. But, interconnecting nano-devices into complex electronic systems has not yet been demonstrated. In this paper, the authors propose a nanocore/CMOS hybrid system-on-package (SoP) architecture which is suitable for any emerging nanotechnology

Keywords

CMOS integrated circuits; hybrid integrated circuits; integrated circuit design; integrated circuit interconnections; nanoelectronics; system-in-package; CMOS hybrid system-on-package; nanocore hybrid system-on-package; nanodevice interconnection; nanoelectronic systems; nanotechnology; semiconductor device fabrication; subnanometre scale; Cellular neural networks; Computer architecture; Delay; Electrons; Fabrication; Information technology; Integrated circuit interconnections; Microelectronics; Nanoscale devices; Scalability; AET cell; error-tolerant; hybrid; nanocore; nanoelectronic; system-on-package;

fLanguage

English

Publisher

ieee

Conference_Titel

High Density Microsystem Design and Packaging and Component Failure Analysis, 2005 Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-9292-2

Electronic_ISBN

0-7803-9293-0

Type

conf

DOI

10.1109/HDP.2005.251425

Filename

4017466