Title :
A case study of system synthesis with non-synthesizable components using extended VHDL
Author :
Babcock, J. D Sterling ; Dollas, Apostolos
Author_Institution :
Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
Abstract :
Extensions to VHDL have been defined in order to produce a compiler that allows for system design with synthesizable and non-synthesizable multi-chip subsystems. The compiler has been completed and this paper presents a case study that has been made to evaluate the merits and limitations of this approach. Finally, a brief discussion is made of the error generation. Capability that results from the use of formal methods in the definition of the VHDL language extensions
Keywords :
hardware description languages; logic CAD; logic design; compiler; error generation; extended VHDL; formal methods; multi-chip subsystems; nonsynthesizable components; system synthesis; Computer aided software engineering; Design automation; Design engineering; Design methodology; Hardware; Libraries; Production; System-level design; Testing;
Conference_Titel :
Rapid System Prototyping, 1995. Proceedings., Sixth IEEE International Workshop on
Conference_Location :
Chapel Hill, NC
Print_ISBN :
0-8186-7100-9
DOI :
10.1109/IWRSP.1995.518587
