Ultra-low power delay-insensitive circuit design

This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits in order to solve the problems of the synchronous counterpart, e.g., sleep signal generation, storage element data loss during sleep mode, and sleep transistor sizing. Significant leakage power reduction has been demonstrated by simulation. Due to the flexible timing requirement feature of delay-insensitive circuits, sub-threshold operation can be achieved, which allows for further supply voltage scaling for ultra-low power.