Retention time improvement with angle ion implantation and buffered layer

Author

Jae-Young, Yi ; Yong-Hui, Lee ; Cheon-Hee, Yi

Author_Institution

Dept. of Control Eng. & Inf., Tech. Univ. Budapest, Hungary

Volume

3

fYear

2000

fDate

2000

Firstpage

42

Abstract

In this paper, we propose a novel method of optimizing the impurity concentration in N-junction region to reduce the local field-enhanced thermionic field emission current, resulting in an excellent tail distribution of retention time without trade-offs of cell transistor threshold voltage and operation current. The fabricated device has W/L=15/0.26, NMOSFET, shallow trench isolation, 7.0 nm wet and/or nitride gate oxide

Keywords

DRAM chips; MOS memory circuits; MOSFET; impurity distribution; ion implantation; isolation technology; thermionic electron emission; 7.0 nm; DRAMs; N-junction region; NMOSFET; angle ion implantation; buffered layer; cell transistor threshold voltage; impurity concentration; local field-enhanced thermionic field emission current; nitride gate oxide; operation current; retention time improvement; shallow trench isolation; tail distribution; Etching; Ion implantation; MOSFETs; Plasma temperature; Probability distribution; Random access memory; Tail; Thermionic emission; Threshold voltage; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2000. Proceedings

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-6355-8

Type

conf

DOI

10.1109/TENCON.2000.892219

Filename

892219