• DocumentCode
    2735284
  • Title

    A floating-point fused add-subtract unit

  • Author

    Saleh, Hani ; Swartzlander, Earl E.

  • Author_Institution
    Intel Corp., Austin, TX
  • fYear
    2008
  • fDate
    10-13 Aug. 2008
  • Firstpage
    519
  • Lastpage
    522
  • Abstract
    A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.
  • Keywords
    adders; floating point arithmetic; conventional floating-point adder; floating-point fused add-subtract unit; size 45 nm; Acceleration; Birth disorders; Delay; Digital signal processing; Hardware design languages; Lakes; Power engineering and energy; Power engineering computing; Signal processing algorithms; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
  • Conference_Location
    Knoxville, TN
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-2166-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2008.4616850
  • Filename
    4616850
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2735284