Toggle rate estimation technique for FPGA circuits considering spatial correlation

The interest in low power chips and systems are driven by both business and technical needs. Since power estimation is the foremost step in any low power design, this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4 input LUT based FPGA. Basically there are two methods of power estimation namely simulation based and probabilistic approach. Simulation based approach is more accurate that the later, but this method is computationally very expensive, practically impossible for large circuits. So, probabilistic method is a solution for this problem. They require only one time simulation and hence they are faster. This advantage is available at the cost of loss of accuracy. So this work focuses on improving the accuracy of probabilistic approach by incorporating more statistical parameters related to toggle rate estimation. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping. This method does a power modeling of FPGA circuits under spatial correlation by computing the transitions at each LUT by processing them in topological order. Gate Delays are also considered in this approach.