Study On a Mixed Verification Strategy for IP-Based SoC Design

The demands for more powerful products and the huge capacity of today´ s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification involves in multi-levels: IP level verification, chip level verification, and hardware/software (HW/SW) co-verification. The last one is the key point to the whole verification process, and some of EDA vendors have provided several EDA tools for HW/SW co-verification. In this paper, the author analyses the architecture of co-verification and the weakness of existing EDA tools, then presents a practical verification strategy based on FPGA, which is more flexible and convenient, and more efficient than traditional verification methods whose hardware and software verification are separate. An experimental result, VAD (video add data) SoC verification, is given as well finally