DocumentCode :
2735432
Title :
A New Partitioning Scheme of Parallel VHDL Simulation
Author :
Yue, WU ; Ling, JIAN ; Hong-bin, Yang ; Zong-Tian, LIU
Author_Institution :
Sch. of Comput. Eng. & Sci., Shanghai Univ.
fYear :
2005
fDate :
27-29 June 2005
Firstpage :
1
Lastpage :
4
Abstract :
The static partitioning algorithm and assigning were generally researched respectively, which has largely resulted in the deficiency in the workload balance of the static partitioning. A new partitioning scheme of parallel VHDL simulation is presented in the paper. Partitioning and assigning both are processed just before the simulation in the scheme, and are included in the running phase. Because of this, it strictly requests that the time complexity of partitioning algorithm is minimum. A new static partitioning algorithm, fan-out right partitioning algorithm, which has a lower time complexity and good performance, is presented in the paper. The experiment result shows that the performance of parallel VHDL simulation is improved with this scheme and partitioning algorithm
Keywords :
circuit simulation; hardware description languages; logic partitioning; fan-out right partitioning algorithm; parallel VHDL simulation; partitioning scheme; static partitioning algorithm; time complexity; Algorithm design and analysis; Circuit simulation; Computational modeling; Computer simulation; Concurrent computing; Digital circuits; Hardware design languages; Partitioning algorithms; Software algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density Microsystem Design and Packaging and Component Failure Analysis, 2005 Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9292-2
Electronic_ISBN :
0-7803-9293-0
Type :
conf
DOI :
10.1109/HDP.2005.251452
Filename :
4017493
Link To Document :
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