A High-Speed Memory Interface Architecture for MPEG2 Video Decoder

Motion compensation (MC) routines of MPEG-2 MP@HL video decoding intensively access the video data stored in external memory, thus efficient memory access is critical in the design of decoder chip. In this paper, an advanced architecture of MC is proposed to perform different types of picture prediction modes employed by the MPEG-2 standard and an address translation method is developed for memory interface. In order to relieve the burden of MC, four pixel generators are used to execute bi-prediction and half-pel precision in parallel. Image data fetched from the external frame memory are reused, so that a great amount of frame memory access can be reduced. The features of SDRAM and the fact that all types of MC algorithm have regular memory access patterns are exploited to minimize the number of overhead cycles needed for row activations in array address translation. Compared with the conventional linear translation, array address translation can reduce most of the row activations. The proposed architecture is very effective not only for increasing the speed of memory access but also for improving the performance of MC