Title :
IP Core Design of PLC Microprocessor with Boolean Module
Author :
Mei-hua, Xu ; Feng, Ran ; Zhang-jin, Chen ; Shu-feng, Kang ; Run-guang, Li
Author_Institution :
Sch. of Mech. Eng. & Autom., Shanghai Univ.
Abstract :
This paper presents the IP core design of PLC (programmable logic controller) microprocessor that includes a special Boolean process unit after analysing PLC programming language, instruction execution characteristics and current PLC disadvantage. The novel microprocessor based on RISC architecture for PLC accords with PLCs international standard and its systematic design requirement. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Altera´s EP20K200EFC484. As a microprocessor IP core for PLC, its particular design of memory bit access interface unit and Boolean processor unit can greatly improve the real time performance and stability for PLC, its design scheme and experimental result will contribute to further research and development of relevant products
Keywords :
electronic design automation; field programmable gate arrays; industrial property; integrated circuit design; microprocessor chips; programmable controllers; reduced instruction set computing; Altera EP20K200EFC484; Boolean module; EDA tools; FPGA; IP core design; PLC microprocessor; PLC programming language; PLC stability; RISC architecture; intellectual property; microprocessor IP core; programmable logic controller microprocessor; real time performance; Computer languages; Electrical equipment industry; Electronic design automation and methodology; Field programmable gate arrays; Industrial control; Logic programming; Microprocessors; Programmable control; Reduced instruction set computing; Research and development;
Conference_Titel :
High Density Microsystem Design and Packaging and Component Failure Analysis, 2005 Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9292-2
Electronic_ISBN :
0-7803-9293-0
DOI :
10.1109/HDP.2005.251460
