An Bidirectional IP Wrapper Design for SoC DFT

With the rapid development of IC design methods and manufacturing technologies, the scale of IC is becoming lager and lager, and the design method of system on chip (SoC) has been widely adopted. In the design process of SoC, the test problem is viewed as the bottleneck of the SoC development; and it is a challenge to test the IP (intellectual property) cores which are embedded deeply in the SoC especially. In order to integrate a SoC, the scheme of wrapping IP cores is available, and is applauded by most of IC designers. A standard IP wrapper cell circuit has been presented in the IEEE P1500 standard, but the cell circuit has some shortages in practice yet. This paper analyzes the testable architecture of IP core and the characteristics of some IP wrappers. Finally, an improved bidirectional wrapper cell circuit is presented and is used in the experimental VAD-SoC design. This technique enhances both controllability and observability and increases the fault coverage