Field programmable gate array (FPGA) based baseline JPEG decoder

Image/video compression is one of the major components used in video-telephony, videoconferencing and multimedia-related applications. Compression allows efficient utilization of channel bandwidth and/or storage size. One of the commonly used methods for image and video compression is JPEG (an image compression standard). In our present work, a real time (the first made in Malaysia) JPEG hardware decoder has been successfully designed and implemented using 100,000 gate FPGA (FLEX10K100 from Altera). The fully functional JPEG decoder prototype is capable of decompressing compressed data to achieve a frame rate of 30 frames per second (for a frame size of 320×240 pixels). Currently the design supports gray scale images, but with some modification and addition of tables to handle the chrominance component, the JPEG decoder can easily handle color images. The major components that have been implemented include the 2-dimensional inverse discrete cosine transform, inverse scalar quantizer and the parallel Huffman decoder. Parallelism and pipelining were fully exploited in the design to achieve the high frame rate