An 8 b 52 MHz double-channel CMOS A/D converter for high-speed data communications

Author

Kim, Ju-Hyung ; Hwang, Sung-Wook ; Lee, Seung-Hoon ; Jee, Yong

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

1999

fDate

18-21 Jan 1999

Firstpage

25

Abstract

This paper describes an 8 b 52 MHz CMOS subranging analog-to-digital converter for Integrated Services Digital Network applications. The ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs for an increased throughput rate. The fabricated and measured prototype ADC in a 0.8 μm CMOS process shows nonlinearities less than ±0.4 LSB at an 8 b level with 5 V and 230 mW

Keywords

CMOS integrated circuits; ISDN; analogue-digital conversion; data communication equipment; interpolation; timing; 0.8 micron; 230 mW; 5 V; 52 MHz; 8 bit; CMOS A/D converter; ISDN applications; double-channel CMOS ADC; high-speed data communications; integrated services digital network; subranging analog-to-digital converter; time-interleaved architecture; Analog-digital conversion; Circuits; Data communication; Energy consumption; Industrial electronics; Prototypes; Resistors; Sampling methods; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759701

Filename

759701