A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application

Author

Byeon, Dae-Seok ; Lee, Sung-Soo ; Lim, Young-Ho ; Kang, Dongku ; Han, Wook-Kee ; Kim, Dong-Hwan ; Suh, Kang-Deog

Author_Institution

Flash Memory Dev. Team, Samsung Electron. Co. Ltd., Hwasung

fYear

2005

fDate

1-3 Nov. 2005

Firstpage

13

Lastpage

16

Abstract

This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise

Keywords

NAND circuits; flash memories; interference suppression; memory architecture; transistors; 4 GBytes; 63 nm; 8 Gbytes; 90 nm; MAT-cell-array architecture; NAND flash memory; charge pumps; common source line noise; floating-gate-coupling noise; mass storage application; multilevel cell; noisy effects suppression; page buffer; peripheral circuits; transistors; Cellular phones; Charge pumps; Circuit noise; Consumer electronics; Costs; Digital cameras; Error correction codes; Flash memory; Packaging; Universal Serial Bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9162-4

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251777

Filename

4017519