An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection

Author

Wakabayashi, Shin´ichi ; Koide, Tetsushi ; Toshine, Naoyoshi ; Goto, Mutsuaki ; Nakayama, Yoshikutsu ; Hayya, K.

Author_Institution

Fac. of Eng., Hiroshima Univ., Japan

fYear

1999

fDate

18-21 Jan 1999

Firstpage

37

Abstract

This paper describes an LSI implementation of a genetic algorithm (GA), called the Genetic Algorithm Accelerator (GAA) chip. The GAA chip is an LSI implementation of a GA, in which two types of crossover operators are supported, and the operator to be actually used in the algorithm is not fixed in advance, but dynamically selected for each pair of chromosomes in the algorithm execution. The GAA chip has been designed with the Verilog HDL and simulated with some benchmark functions. According to the simulation, the GAA chip will run with a maximum 50 MHz clock. The chip has been fabricated with CMOS 0.5 μm standard cell technology

Keywords

CMOS digital integrated circuits; VLSI; coprocessors; genetic algorithms; 0.5 micron; 50 MHz; CMOS standard cell technology; VLSI implementation; Verilog HDL; adaptive genetic algorithm; genetic algorithm accelerator chip; on-the-fly crossover operator selection; Biological cells; CMOS technology; Clocks; Field programmable gate arrays; Genetic algorithms; Genetic engineering; Hardware design languages; Large scale integration; Robustness; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759704

Filename

759704